BrainChip Sequora and Akida Silicon IP: A Workload-Split Playbook for Battery-Powered Edge AI SoCs
Ask the teams shipping battery-operated products what blocks local generation, and accuracy is rarely the first answer. The blockers are a memory footprint that stretches with context and the energy tax of pushing every sample to a radio for inference. The BrainChip response is structural rather than incremental: one core absorbs the continuous sensor stream, a second core carries the generative and sequential load, and the state representation behind that second core is deliberately capped. For an engineer who still has time before floorplan freeze, the partition itself is the most actionable idea in the release.
Two roles inside one edge AI subsystem
The pairing is framed as complementary coverage of AI workloads, not as a decision between rival engines. The stated boundaries are as follows.
- Akida, neural processor IP on the perception side — owns streaming sensor data: vibration, audio, radar, raw RF IQ samples and biological signals.
- Sequora, processor IP on the generation side — owns generative and sequential work: on-device large language model (LLM) inference, voice-to-voice interaction and AI agents, executed locally on hardware such as earbuds and sensor nodes.
Because the seam follows the shape of the data rather than a marketing label, the first question for a design team is simple: which traffic dominates the product, continuous telemetry or dialogue and generation. In most earbud and node concepts both classes exist, which is precisely the scenario this dual-core arrangement is positioned for.
Architecture properties that belong in the budget
A state that stops growing
Sequora is optimised for state-space models (SSMs). An SSM represents input history through a fixed-size state, so memory demand holds steady while the sequence lengthens. On a battery-powered die where SRAM cannot be added after the fact, that flat curve — not headline model capability — is what converts local generation from a demo into a schedulable design item.
One array covering maths and networks
Signal processing and neural-network computation run on a unified multiply-accumulate (MAC) array. The consequence for the block diagram is concrete rather than rhetorical: no separate DSP preprocessing stage sits in front of the network. That removes one data mover between the sensor path and the model, one verification domain, and one island that would otherwise need its own clocking and power treatment.
An instruction set that keeps the part updatable
The instruction-set architecture (ISA) is specified as allowing new algorithms to be deployed through software updates. Workload coverage therefore need not be frozen at tape-out, which is the standard objection against hard-wired edge inference and the reason firmware headroom should be reserved at planning time.
Attributes and counts as stated
| Item | As stated in the material | What it means on the die |
|---|---|---|
| Memory scaling versus sequence length | Constant, because an SSM keeps a fixed-size state | SRAM reservation becomes a fixed line item instead of a worst-case guess |
| Separate DSP preprocessing stage | Not required; a unified MAC array covers both | One fewer hand-off, one fewer power and clock domain |
| Streaming data classes on Akida | Five: vibration, audio, radar, raw RF IQ, biological signals | Sets the expected front-end sensor mix for the subsystem |
| Workload classes on Sequora | Generative and sequential, including LLM inference, voice-to-voice interaction, AI agents | Defines the top of the on-device software stack |
| Reference hardware | Battery-powered edge devices, earbuds and sensor nodes named | Anchors the energy envelope the IP is tuned to |
| Delivery form | Process-portable, fully synthesizable RTL | Re-targeting between processes is a flow exercise, not a redesign |
| Collateral bundled with the core | Verification IP, synthesis scripts, SDK | The three line items that actually consume integration schedule |
| Named SDK elements | Three: compiler, C++ runtime library, model zoo | Determines how a trained model reaches silicon |
| Licensing status | Available now as licensable semiconductor IP from Brainchip Holdings | Design-in evaluation can start immediately |
Akida and Sequora side by side
| Dimension | Akida | Sequora |
|---|---|---|
| Position in the subsystem | Streaming perception engine | Generative and sequential engine |
| Data and tasks handled | Vibration, audio, radar, raw RF IQ data, biological signals | On-device LLM inference, voice-to-voice interaction, AI agents |
| Architecture emphasis | Not detailed in the released material | Optimised for SSMs on a unified MAC array |
| Behaviour as sequences lengthen | Not detailed in the released material | Memory requirements stay constant thanks to the fixed-size state |
| Algorithm refresh path | Not detailed in the released material | New algorithms deployable through software on the ISA |
| Relationship to the partner core | Covers the complementary workload Sequora does not target | Covers the complementary workload Akida does not target |
Licensing, delivery and integration reality
Sequora is offered as licensable semiconductor IP from Brainchip Holdings in process-portable, fully synthesizable RTL form. Alongside the RTL, the delivery bundle lists verification IP, synthesis scripts and an SDK built around a compiler, a C++ runtime library and a model zoo. Read from a program-management angle, the IP travels between processes while the scripts, the verification collateral and the toolchain remain project work: they are the items that absorb engineer-hours, and they should appear as tasks in the integration plan rather than as assumed inclusions.
Design-in checklist
- Classify the dominant traffic: continuous sensor streams fall to Akida, generative or sequential jobs fall to Sequora.
- Test the concept against the stated envelope: battery-powered edge hardware, with earbuds and sensor nodes as the reference examples.
- Rebuild the memory plan on the constant-state assumption rather than on per-token growth, and re-derive the SRAM figure.
- Decide whether the unified MAC array lets you delete the DSP preprocessing stage from the partition and the verification scope.
- Scope the synthesis scripts and verification IP as schedule items sized for your own flow, not as finished evidence.
- Reserve firmware and flash headroom so new algorithms can arrive through the ISA software path instead of a respin.
- Validate toolchain fit early: compiler flow, C++ runtime footprint, and whether the shipped model zoo already covers the SSM families you intend to run.
Common misconceptions
- Sequora displaces Akida. The two are positioned as complementary halves; the perception core stays in the subsystem.
- A fixed-size state guarantees answer quality. The claim is about memory behaviour as sequences lengthen, not an accuracy statement.
- No DSP stage means no signal processing. Signal processing still happens — it happens on the same MAC array, which is exactly why a discrete preprocessing stage leaves the diagram.
- Edge generation still needs a modem. The stated intent is local execution on battery-powered devices, earbuds and sensor nodes included.
- Synthesizable RTL equals turnkey silicon. Portability describes the source; node-specific synthesis, verification sign-off and SDK enablement remain on your schedule.
Recommended next actions
- Score every concept on a two-axis grid — streaming load versus generative load — before assuming a single accelerator is enough.
- Model the state memory of a candidate SSM as a constant and check the residual budget against your power envelope.
- Treat removal of the DSP preprocessing stage as a real floorplanning saving and reallocate it toward sensor interface or radio logic.
- Request the licensable core evaluation path from Brainchip Holdings and pull the RTL, scripts and collateral into a scoped pilot.
- Write the field-update plan now, since the ISA-based software deployment of new algorithms is the mechanism that protects the design over its product life.
- Gate the pilot on the model zoo: if your target SSM family is absent, the toolchain gap becomes the critical path rather than the array itself.
FAQ
Can an LLM genuinely execute with no connectivity?
That is the stated purpose of Sequora: local generative AI and LLM inference on battery-powered edge devices, with earbuds and sensor nodes named as examples.
Which core sees raw audio?
Continuous streams, audio among them, sit with Akida. Sequora takes over at the generative layer, where voice-to-voice interaction and AI agents run.
Why SSMs rather than any other model family?
Input history lives in a fixed-size state, so memory requirements hold steady as sequences grow — the constraint that usually rules generation out on small hardware.
Is a DSP front end still required?
No separate DSP preprocessing stage is required, because the unified MAC array performs signal processing together with neural-network computation.
How is the core obtained, and in what form?
Sequora is available now as licensable semiconductor IP from Brainchip Holdings, delivered as process-portable, fully synthesizable RTL together with verification IP, synthesis scripts and an SDK.
Bottom line for semiconductor planners
The useful signal here is not another accelerator announcement; it is the acknowledgement that edge AI now contains two different data physics and should be partitioned accordingly. Perception streams and generation belong on separate engines, while the capped state and the shared MAC array are the two architectural levers that let generation fit inside a coin-cell budget. Teams evaluating this path should benchmark the memory curve, the deleted preprocessing stage and the SDK coverage before committing the partition — and should keep the software update channel in the plan, because the models that ship in year two are rarely the ones compiled at first silicon.
Prepared by Rachel Williams for the Semiconductors desk at Electronicseng, Electronics & Engineering. Editorial contact: info@electronicseng.com.