By Rachel Williams — Electronicseng, Semiconductors desk
Capacity headlines are cheap; tester utilization is not. With five semiconductor plants in India now shipping commercially, the binding constraint on outsourced assembly and test is no longer cleanroom floor space or the number of lines on a floor plan — it is the count of minutes each device spends on a tester. SEMI’s July 2026 forecast sets the supply-side backdrop: global semiconductor test equipment sales are projected to climb 31% to $15.3 billion in 2026, after 55.3% growth in 2025, and to reach $20.8 billion in 2028. Read from an OSAT operations chair, those dollars translate into lead times, qualification windows and test architectures, and that is where this Electronicseng analysis focuses.
| Reference year | Test equipment signal (SEMI) | Planning implication for assembly and test |
|---|---|---|
| 2025 | 55.3% growth | Test capital has already been re-rated from back-end afterthought to scheduled spend |
| 2026 | 31% rise to $15.3 billion | New line capacity only converts to shipped parts if testers are qualified in parallel |
| 2028 | $20.8 billion | Platforms chosen today will still be in service, so headroom and upgrade path carry cost |
The inference Electronicseng draws is deliberately narrow: a rising tester spend curve is a symptom of the bottleneck, not proof that it has been solved. An OSAT serving several device families at once has to qualify equipment per device type, hold test coverage while retiring legacy platforms, and, for brand-new silicon, invent an architecture that does not yet exist.
A facility that states it can produce 15 million chips a year has told investors something and engineers very little. The identical headline output can be assembled from a fleet running each device under a minute or one spending five to 10 minutes on every unit, and those two worlds demand materially different equipment populations.
The clearest public datapoint arrived in September 2025, when Emerson announced a partnership with Kaynes Semicon to deploy the NI Semiconductor Test System (STS) as the primary test platform at Kaynes’ OSAT facility in Sanand, Gujarat. In the interview recorded by EE Times and reviewed for this Electronicseng column, Karthik Balasekar, chief business manager for semiconductor and electronics, and Ved Mahanta, principal account manager — both at NI India, part of Emerson — laid out both the arithmetic and the procurement clock behind a decision of that kind.
Mahanta positioned qualification as the gate rather than a formality: “Customers typically conduct tester qualification before making a final purchasing decision,” and measured that window in six months to one year. On the Gujarat site he was explicit: “The process generally takes six months to one year. In the case of Kaynes, we can publicly state that the company has decided to proceed with NI testers. We are in the process of delivering the testers in the coming months.” Discussions with other OSAT facilities continue, he added, many still qualifying equipment, with NI unable to name companies whose engagements had not been publicly disclosed.
Tester count, according to Balasekar, collapses to two inputs: per-device test time and the production target. “Facilities handling millions of devices may need fewer testers if each test takes less than a minute,” he explained, whereas “Testing complex chips that require five or 10 minutes per device could demand more equipment to meet the same production target.” For simpler parts, pin count plus the required test items govern cycle time; fewer pins and lighter requirements let the same instrument push more devices per shift.
Announced capacity must also be parsed as a sum instead of a rate. “An OSAT might announce an annual capacity of 14 million or 15 million chips, for example. Such figures generally represent the combined output capacity of its production lines, whether the facility operates 10 lines, 50 lines, or another number,” Mahanta said. NI Emerson has published no test-system count for Kaynes, and he compared OSAT capacity statements with vehicle output claims from automotive plants, adding that “Actual production depends on customer demand,” not the figure printed on a press release.
Inside the line, the objective is throughput with confidence — the most devices in the shortest window, each confirmed against specification. TestStand, NI’s test automation platform, is the layer that sequences those operations so batch disposition decisions arrive faster.
| Planning variable | Simple, high-volume device | Complex, long-duration device | Consequence for the tester fleet |
|---|---|---|---|
| Per-device test time | under a minute | five to 10 minutes | Identical output targets map to very different equipment counts |
| Pin count and test items | Fewer pins, lighter test requirements | Heavier test set per device | Cycle time rises, so parallelism has to compensate |
| Device family mix | Mixed-signal products today | RF products later, on the same STS | Platform reuse protects capital when the tester spans both |
| Architecture status | Legacy device on an older platform with insufficient throughput | New product with no legacy technical debt | Migration against fixed coverage targets versus a ground-up build |
Balasekar framed Kaynes’ selection as a portfolio question rather than a single-device one. “Our STS is a platform that supports both mixed-signal and RF applications,” he said. “For example, if Kaynes tests mixed-signal products today and moves to RF products later, it can reuse the same STS tester for different devices under test.”
Flexibility alone, however, does not settle the architecture. Mahanta divides inbound work into two classes: “Typically, customers want to test two types of devices: legacy devices and new products, commonly referred to as new product development,” with legacy lines often running on platforms that no longer deliver the throughput the target requires. “OSATs need to move these products to newer systems without compromising test coverage,” he said, noting that customers usually complete much of the preparatory work themselves and specify what the OSAT must test.
Fabless startups invert that division of labour. “Some Indian startups developing their own chips have never performed final testing and depend on the OSAT to guide them,” Mahanta said. “The OSAT must help determine how to test each device reliably and quickly enough to meet production and time-to-market requirements.” Even where no legacy technical debt exists, the assembly and test house may still have to construct the architecture from zero — “This includes determining the test requirements, selecting an appropriate system, and ensuring that it meets test coverage and throughput targets,” he said, with the neutral caveat that “Such a system could come from NI Emerson or another test equipment supplier.” Both problems sharpen as design complexity rises, Balasekar added.
Modularity is the standing mitigation. Mahanta pointed to PXI (PCI eXtensions for Instrumentation) systems, which let a customer add modules for newly required tests without altering existing test parameters: “Customers can expand their testing capabilities as their requirements evolve,” he said.
For new devices, NI has begun applying AI upstream of the bench. Mahanta described an engineer uploading a chip’s datasheet to NI’s Nigel AI test development tool, which examines selected parameters and proposes a potential test architecture. “The engineer could then use the suggested framework as a starting point rather than developing the entire architecture from scratch,” he explained, and was careful about scope: “This approach targets part of the work involved in test development, rather than replacing the validation engineer,” because “AI could take on some repetitive tasks, leaving engineers to focus on more complex problem-solving.”
Under India Semiconductor Mission 2.0 (ISM 2.0), Ashwini Vaishnaw said at SEMICON India 2026 that government focus will span six areas, among them advanced packaging and testing units and talent. For OSATs, that phrasing makes three capabilities measurable: test-system flexibility, device qualification throughput, and the capacity to absorb different device requirements in the same facility.
Mahanta said NI has invested in local engineering capability so its engineers can support OSAT customers on site, reducing the need to bring specialists in from Taiwan and Singapore, and cited Tessolve, an NI partner serving customers globally, as an example of an Indian company already participating in the testing ecosystem. “There are integrated device manufacturers that base 40% to 50% of their product lines in India,” he said, adding that “Building engineering expertise will be essential for Indian companies seeking to serve global semiconductor manufacturers.”
Balasekar’s worry is labour supply rather than capital: growth in OSATs and electronics manufacturing could outpace the availability of skilled workers as electronic device exports and the mobile phone manufacturing base expand, and he looks to the workforce development component of ISM 2.0 to close the gap. “I think that will help India grow faster and keep pace with the market’s expansion,” he said.
Test time per device. A target stated as 15 million chips a year maps to completely different fleets of instruments depending on whether each unit is measured under a minute or occupies the tester for five to 10 minutes.
Six months to one year per Mahanta. Because “Customers typically conduct tester qualification before making a final purchasing decision,” the qualification window, not the equipment list price, usually sets the schedule.
That is NI’s stated design intent for STS: the same tester can be reused for different devices under test as a customer’s product mix moves between families.
At the drafting stage. A datasheet goes into Nigel AI, a candidate architecture comes out, and the engineer uses that framework as a starting point — the validation engineer is not displaced.
It signals supplier-side expansion and a busier installation pipeline, but it does not shorten qualification, nor does it fix coverage targets that have not been defined.
For Electronicseng readers who own assembly and test roadmaps, the conclusion is a scheduling one: the interesting number in any Indian capacity announcement is not the chip count but the minutes each chip spends under test. Equipment budgets will keep expanding along the SEMI curve, while the plants that convert that spending into shipped silicon will be the ones that sized their testers by cycle time, qualified early against the two device classes they already serve, and bought modularity for the requirements they have not yet met.