Inside the Semiconductor Shift: Synaptics Astra SR200 xMCU Memory Tiering and Coralboard Selection for Edge AI

For teams building multimodal inference products, the memory subsystem is usually where the power budget and the bill of materials collide. Synaptics has put forward its answer with the xMCU category, which the company describes as a new microcontroller class for multimodal edge AI that keeps voice, vision, audio, motion, and contextual sensing inside the device. Unveiled during the vendor's annual tech day, the Astra SR200 series combines heterogeneous AI-native compute and acceleration with integrated high-bandwidth custom DRAM, while the Coralboard family brings the same foundation to evaluation hardware. The breakdown below looks at the architecture logic, the parameter spread across the three versions, the software path, and the practical selection criteria for engineers and sourcing professionals.

Why memory tiering defines the SR200 Series

According to Synaptics, the tiered architecture pairs up to 8 MB of SRAM with extensible, high-bandwidth, high-capacity custom DRAM that can scale to hundreds of megabytes as AI models and workloads require. The company states that the design executes workloads at one-third the power of typical system DRAM, removing the need for external memory in most applications while using only a fraction of system power.

Read as a semiconductor decision rather than a headline claim, this moves capacity from board layout into the silicon itself. That is what allows larger AI models and multimodal workloads to operate entirely on-device, and it explains the target set the vendor names: AI wearables, battery-powered sensing devices, connected cameras, streamers, and industrial vision and voice systems.

The six core vectors behind the platform

According to Synaptics, the Astra SR200 series is organized around several core vectors that increase design flexibility: high-performance compute with extensible memory, transformer-ready AI acceleration, silicon-rooted security, multimodal integration, an ultra-low-power architecture with tiered domains, and an open-source software ecosystem.

To extend scalability, the xMCU series is offered in three versions. They are pin-compatible and share a common hardware foundation and software development kit (SDK), which means a product can move between compute tiers without inventing a second board architecture.

Version comparison: compute tier against workload profile

Version	Compute	Use case
SR210	200 GOPS	power-optimized, always-on voice and sensing
SR230	300 GOPS	vision, display, and optional audio for mainstream multimodal devices
SR250	400 GOPS	dual vision and display paths for premium edge applications

Astra SR200 xMCU (Source: Synaptics Inc.)

Compute engines and the accelerator stack

The SR200 Series uses the Synaptics Torq AI engine, a standards-based hardware architecture and unified developer experience that integrates the Coral NPU from Google Research. Synaptics said the engine is optimized for low-latency, high-efficiency execution of deep learning workloads, including CNN, transformer, and fully connected networks, and that the open-source MLIR/IREE compiler supports industry-standard frameworks and model formats.

On the control side, the series claims the industry’s first pairing of the Arm Cortex-M85 and Cortex-M52. Scaling to 800 MHz, the high-performance core handles control, multimedia, and burst-compute workloads; the efficiency core provides always-on sensor fusion, connectivity, and low-power inference. An optional Cadence Tensilica HiFi 5 DSP is available for dedicated audio and acoustic ML processing, while an always-on domain manages voice activity detection, timekeeping, and wake-up.

Security posture and interface coverage

Security is built on a multi-layered security engine that combines hardware isolation, cryptographic acceleration, anti-tamper detection, device lifecycle management, and secure boot. The vendor states the series meets PSA Level 3 and CC EAL4+ certification targets, providing protection against software and physical attacks.

For flexibility, the platform offers a wide range of peripherals and connectivity, including high-speed octal SPI, SDIO, and eMMC storage interfaces, plus UART, SPI, I2C, I3C, PWM, USB 2.0, and low-power GPIOs. Industrial variants provide 1Gb Ethernet with IEEE 1588 TSN support and two CAN-FD interfaces, enabling deterministic networking and real-time industrial control for physical AI and robotics applications. In addition to the open-source Torq NPU compiler, the platform supports Zephyr RTOS.

Coralboard SR development board: baseline parameters

Synaptics also introduced the Coralboard SR development board, which is based on the new SR200 Series. Developed with Google Research, the Coralboard family offers an edge AI developer experience across the SL and SR versions through the MLIR-based Synaptics Torq compiler and runtime. The boards provide open hardware and software for edge AI applications, including wearables, hearables, smart home appliances, automation hubs, industrial control systems, and robotics.

According to Synaptics, the Torq open-source toolchain supports popular ML frameworks and is designed to provide day-0 support for edge AI model families such as Google Gemma3 270M, which achieves up to 12-16 tokens/second with INT8 and 4-bit quantization respectively, LiquidAI LFM2.5, and Ultralytics YOLO26. It uses active-research techniques such as batch-prefill and dynamic quantization.

Key features of the Coralboard SR include the Astra SR250 Series with 800-MHz Arm Cortex M85, Cortex M52, 400 GOPS Torq/Coral NPU, NOR flash memory, a microSD card slot, integrated SRAM up to 8 MB, and high-bandwidth custom DRAM up to 256 MB. The board also includes Wi-Fi/Bluetooth connectivity, QWICC and mikroBUS connectors, and multi-camera and display support via CSI/DSI and USB, as well as support for dual ISPs and digital mics.

Coralboard development board (Source: Synaptics Inc.)

Coralboard SR and Coralboard SL side by side

Attribute	Coralboard SR	Coralboard SL
Silicon on board	Astra SR250 Series	Astra SL2619
Processor cores	800-MHz Arm Cortex M85 plus Cortex M52	2× 2-GHz Arm Cortex A55 plus Cortex-M52
Acceleration	400 GOPS Torq/Coral NPU	1-TOPS Synaptics Torq NPU; first implementation of the Coral NPU
Memory	Integrated SRAM up to 8 MB; high-bandwidth custom DRAM up to 256 MB	2-GB DDR4
Storage	NOR flash memory, microSD card slot	NOR flash memory
Expansion	QWICC and mikroBUS connectors; multi-camera and display via CSI/DSI and USB; dual ISPs and digital mics	Add-on HATs for HDMI display, power, camera, and digital mics; QWICC and mikroBUS connectors; multi-camera and display via CSI/DSI and USB; dual ISPs and digital mics
Wireless	Wi-Fi/Bluetooth	Wi-Fi/Bluetooth

Coralboard SL availability and ordering window

Synaptics also announced that the Coralboard SL is now generally available through DigiKey. It is powered by the Astra SL2619, which integrates the 1-TOPS Synaptics Torq NPU and is also the first implementation of the Coral NPU.

Key features of the Coralboard SL include the Astra SL2619 with 2× 2-GHz Arm Cortex A55, Cortex-M52, 1-TOPS Torq/Coral NPU, 2-GB DDR4, NOR flash memory, and add-on HATs for HDMI display, power, camera, and digital mics. Like the Coralboard SR, it also includes Wi-Fi/Bluetooth connectivity, QWICC and mikroBUS connectors, and multi-camera and display support via CSI/DSI and USB, as well as support for dual ISPs and digital mics.

The Synaptics Coralboard is available to order from DigiKey starting October 20, 2026.

Common misconceptions before you commit

• "Higher GOPS automatically means the right part." The three versions are tiered by workload profile, not only by throughput: SR210 at 200 GOPS is described as power-optimized for always-on voice and sensing, while SR250 at 400 GOPS is positioned for dual vision and display paths in premium edge applications.
• "Multimodal inference still needs a separate memory device on the board." The architecture pairs up to 8 MB of SRAM with custom DRAM that can scale to hundreds of megabytes, which Synaptics says removes the need for external memory in most applications and runs at one-third the power of typical system DRAM.
• "Evaluation hardware is detached from production silicon." The Coralboard SR development board is based on the new SR200 Series, the Coralboard SL runs the Astra SL2619, and the xMCU series parts are pin-compatible with a shared SDK.
• "Security can be retrofitted entirely in firmware." The SR200 combines hardware isolation, cryptographic acceleration, anti-tamper detection, lifecycle management, and secure boot inside the silicon, with stated PSA Level 3 and CC EAL4+ certification targets.
• "Toolchain support means any model hits the published speed." The up to 12-16 tokens/second figure is tied to Google Gemma3 270M under INT8 and 4-bit quantization respectively, and day-0 support is described per model family, alongside LiquidAI LFM2.5 and Ultralytics YOLO26.

Selection checklist for engineers and buyers

• Map the modal set first: which of voice, vision, audio, motion, and contextual sensing the product actually executes, since that determines the tier.
• Quantify memory growth against the tiered architecture — up to 8 MB SRAM and custom DRAM scaling to hundreds of megabytes — rather than defaulting to an external memory device.
• Split the power review: voice activity detection, timekeeping, and wake-up sit in the always-on domain, while sensor fusion and low-power inference sit on the efficiency core, and burst-compute, control, and multimedia sit on the core scaling to 800 MHz.
• Validate the audio path as a separate decision, because dedicated acoustic ML processing requires the optional Cadence Tensilica HiFi 5 DSP.
• Confirm interface coverage early: high-speed octal SPI, SDIO, eMMC, UART, SPI, I2C, I3C, PWM, USB 2.0, and low-power GPIOs.
• For industrial programmes, verify that the industrial variants are specified, since only they provide 1Gb Ethernet with IEEE 1588 TSN support and two CAN-FD interfaces.
• Test the software assumptions against the MLIR/IREE compiler, the Torq NPU compiler, and Zephyr RTOS support.
• Match the certification posture — PSA Level 3 and CC EAL4+ targets — to your own threat model before design-in.
• Check distribution through the channel named by the vendor, DigiKey, and align prototypes with the announced order window.

Action recommendations

1. Prototype on the Coralboard family rather than on datasheet arithmetic, so the stated throughput figures can be reproduced with your own models before a tier is chosen.
2. Plan an upgrade lane inside the xMC series from the start: the three versions are pin-compatible and share a common hardware foundation and SDK, so a design can be re-tuned without a new board family.
3. Treat memory scaling as the primary sizing exercise, using the tiered SRAM and custom DRAM headroom (up to 256 MB on the Coralboard SR board) instead of adding board-level DRAM to the bill of materials.
4. If deterministic networking or real-time control is in scope, validate the industrial variants early against 1Gb Ethernet with IEEE 1588 TSN support and two CAN-FD interfaces.
5. Track model support through the MLIR-based Synaptics Torq compiler and the Torq open-source toolchain, since day-0 coverage is published per model family.
6. Place evaluation orders inside the announced window: the Synaptics Coralboard is available to order from DigiKey starting October 20, 2026.

Data points and who reports them

Because nearly every quantitative statement around this launch is vendor-reported, engineering teams should treat the following as claims to verify on their own workloads.

• Power and memory scaling — one-third the power of typical system DRAM, up to 8 MB SRAM, custom DRAM to hundreds of megabytes: stated by Synaptics at its annual tech day.
• Compute tiers of 200 GOPS, 300 GOPS, and 400 GOPS, and the 800 MHz ceiling on the Arm Cortex-M85: Synaptics product information.
• Model throughput of up to 12-16 tokens/second for Google Gemma3 270M with INT8 and 4-bit quantization respectively: cited by Synaptics for the Torq open-source toolchain.
• Certification targets of PSA Level 3 and CC EAL4+: statements attributed to Synaptics Inc.
• Accelerator lineage: the Coral NPU from Google Research, integrated through the Synaptics Torq AI engine, with the Astra SL2619 described as the first implementation of the Coral NPU.
• Availability and pricing channel: general availability of the Coralboard SL through DigiKey, and orders opening on October 20, 2026.

FAQ

What does xMCU mean in practical terms?

Synaptics positions the xMCU as a new microcontroller class for multimodal edge AI. In the Astra SR200 series that means heterogeneous AI-native compute and acceleration combined with integrated high-bandwidth custom DRAM, so device-native, real-time experiences can bring together voice, vision, audio, motion, and contextual sensing.

How do the three versions differ from each other?

All of them are pin-compatible and share a common hardware foundation and SDK. The differentiation is compute against workload profile: SR210 at 200 GOPS for power-optimized always-on voice and sensing, SR230 at 300 GOPS for vision, display, and optional audio in mainstream multimodal devices, and SR250 at 400 GOPS for dual vision and display paths in premium edge applications.

Is external memory required for larger models?

Not in most applications, according to Synaptics. The tiered architecture pairs up to 8 MB of SRAM with high-bandwidth custom DRAM that scales to hundreds of megabytes, executes at one-third the power of typical system DRAM, and thereby removes the need for external memory while using only a fraction of system power.

Which NPU sits behind the engine, and what can developers compile for it?

The Synaptics Torq AI engine integrates the Coral NPU from Google Research. Compilation runs through the open-source MLIR/IREE compiler and the Torq NPU compiler, and the platform also supports Zephyr RTOS. The Torq open-source toolchain is designed to give day-0 support to Google Gemma3 270M, LiquidAI LFM2.5, and Ultralytics YOLO26.

Where do the two development boards diverge?

The Coralboard SR development board is built on the Astra SR250 Series, an 800-MHz Arm Cortex M85 with Cortex M52, a 400 GOPS Torq/Coral NPU, SRAM up to 8 MB, and custom DRAM up to 256 MB. The Coralboard SL runs the Astra SL2619 with 2× 2-GHz Arm Cortex A55, Cortex-M52, a 1-TOPS Synaptics Torq NPU, and 2-GB DDR4, plus add-on HATs for HDMI display, power, camera, and digital mics. Both expose Wi-Fi/Bluetooth connectivity, QWICC and mikroBUS connectors, and multi-camera and display support via CSI/DSI and USB, with dual ISPs and digital mics.

Who distributes the boards, and from when?

The Coralboard SL is generally available through DigiKey, and the Synaptics Coralboard is available to order from DigiKey starting October 20, 2026.

Taken together, the launch matters less for a single throughput number than for where memory now sits in the power tree. For semiconductor planners the real question is whether tiered SRAM, extensible custom DRAM, transformer-oriented acceleration, and an open-source compilation path change the calculation for battery-powered multimodal products. The Astra SR200 series and the Coralboard family give engineers an evaluation route to answer that with their own models before any production commitment.